The present invention relates to a BPSK (Binary Phase-Shift Keying) Costas-type PLL (Phase-Locked Loop) circuit in which false locking, and consequently a high bit error rate, is prevented.
FIG. 1 of the accompanying drawings depicts a BPSK Costas-type PLL circuit of a configuration that has been widely used in the prior art. A BPSK modulated signal at IF (Intermediate Frequency) received on a line 10 is split into two parts, which are applied to first inputs of respective balanced mixers 11 and 12. The mixers 11 and 12 may be implemented, for instance, as double-balanced diode mixers. Second inputs of the mixers 11 and 12 receive as reference signals to the respective mixers 90.degree. and 0.degree. outputs from a voltage-controlled oscillator 14. The outputs of the mixers 11 and 12 are applied through respective data low-pass filters 13 and 16 and thence through amplifiers 17 and 21. The output of the amplifier 17 in the 90.degree. leg is applied directly to one input of a multiplier 22, while the other is passed through a limiter 21 before being applied to the other input of the multiplier 22. The data output of the circuit is also provided by the output of the limiter 21. The output of the multiplier is applied through a loop filter 15 to the voltage control input of the voltage-controlled oscillator 14. A sweep generator 23 is connected through a switch 24, which may be an FET (Field-Effect Transistor) switch, to the junction between the loop filter 15 and the voltage-controlled oscillator 14.
In operation, demodulation of the input BPSK signal to baseband is accomplished in the mixers 11 and 12 by mixing the BPSK signal with the 0.degree. and 90.degree. output signals from the voltage-controlled oscillator. These 0.degree. and 90.degree. signals are coherent recovered signals at the IF frequency. The mixer 12 driven by the 0.degree. signal outputs bipolar data, which is passed through the low-pass filter 16 to remove higher-order mixing products and the normally present channel noise. The bandwidth of the filter 16 should be about the same as the symbol rate of the data to be recovered. On the other hand, the mixer 11 driven by the 90.degree. signal outputs a signal that contains a data signal component which is proportional to the amount of phase error between the IF signal and the coherent recovered carrier. This error signal is passed through the filter 13, which is identical to the filter 16 in the 0.degree. arm of the circuit. After passing through the limiter 21 (which is provided to allow a less critical design of the multiplier circuits), this signal is multiplied with the error signal provided on the output of the amplifier 17 by the multiplier 22. The resulting product signal, which has an amplitude proportional to the phase error and a polarity corresponding to the direction of the phase error (positive or negative), drives the loop filter 15, thereby to establish the phase-locked loop bandwidth. The output of the loop filter 15 controls the frequency of the 0.degree. and 90.degree. signals produced by the voltage-controlled oscillator 14.
When the circuit is put into operation, due to its narrow bandwidth, it is necessary to achieve initial phase lock with the input BPSK signal. For this purpose, the switch 24 is closed and the sweep generator 23 swept in frequency until locking is detected. At that time, the switch 24 is opened, allowing the circuit to operate in the manner described above.
However, sometimes false locking of the circuit may occur. This happens especially when the received signal has a frequency error of the same order as the symbol rate of the data it carries.
More specifically, during the initial lock-in procedure, the frequency of the sweep generator 23 is swept through the expected range of uncertainty of the input signal to cause the narrow bandwidth PLL circuit to lock itself on to the input signal. If though the combined IF error and voltage-controlled oscillator offset due to the sweep are equal to the symbol rate, false locking will occur. In such a condition, the bit error rate of the data signal on the output of the limiter 21 will be very high, even though there is little or no channel noise present. This is a distinct drawback with this circuit.
Another drawback is that there must be some further circuitry (not shown in FIG. 1 but of well-known design) provided to detect when lock-in occurs, which circuitry is unavoidably complex.